NMOS PIPELINED IMAGE PROCESSOR USING QUATERNARY LOGIC.

Michitaka Kameyama, Takahiro Hanyu, Masayoshi Esashi, Tatsuo Higuchi

Research output: Contribution to journalConference articlepeer-review

3 Citations (Scopus)

Abstract

Summary form only given. The implementation of a NMOS chip for 4-valued pipelined image processing using quaternary logic is discussed. The image processing algorithm is based on cellular logic operations which are performed digitally to transform an array of 4-valued input data into a new data array. With images having 4 levels, each pixel can be directly expressed by a single quaternary digit. It has been found that by the use of quaternary logic, systematic image processing can be achieved effectively without going back and forth between the actual image and the binary data.

Original languageEnglish
Pages (from-to)86-87, 315
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 1985 Dec 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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