An overview of fully silicided (FUSI) gates, with emphasis on Ni-based materials for applications into 45 nm and sub-45 nm CMOS nodes is presented. The work function (WF) of FUSI gates for a variety of cases and conditions was investigated, finding lower WF values (suitable for NMOS) for 1) gate stacks containing lanthanides (such as Yb) for SiON or HfSiON, 2) NiSi with dopants (Sb, As and P) on SiO2 or SiON and 3) Si-richer suicides (e.g. monosilicides) for HfSiON. Higher WF values (adequate for PMOS) were found for 1) Pt containing suicides on SiO2 or SiON, 2) Ni or Pt metal-rich suicides on HfSiON and 3) B doped NiSi or Al doped Ni-rich silicides on SiO 2 or SiON. Several of these FUSI gates were implemented in transistors demonstrating |Vt| values down to ∼0.25-0.3 V. The scalability and integration issues are discussed, demonstrating good device characteristics down to ∼50 nm gate lengths for optimized process conditions. Finally, a dual WF Ni FUSI CMOS integration flow is demonstrated. copyright The Electrochemical Society.