Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS

S. Kubicek; A. Veloso; K. G. Anil; S. Hayashi; K. Yamamoto; R. Mitsuhashi; A. Kittl; M. Lauwers; S. Van Dal; Horii; Y. Harada; M. Kubota; M. Niwa; S. De Gendt; M. Heyns; M. Jurczak; S. Biesemans

doi:10.1109/VTSA.2005.1497094

Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS

S. Kubicek, A. Veloso, K. G. Anil, S. Hayashi, K. Yamamoto, R. Mitsuhashi, A. Kittl, M. Lauwers, S. Van Dal, Horii, Y. Harada, M. Kubota, M. Niwa, S. De Gendt, M. Heyns, M. Jurczak, S. Biesemans

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like C_inv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the V_DD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.

Original language	English
Title of host publication	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
Pages	99-100
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2005.1497094
Publication status	Published - 2005 Oct 31
Externally published	Yes
Event	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan, Province of China Duration: 2005 Apr 25 → 2005 Apr 27

Publication series

Name	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Other

Other	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
Country	Taiwan, Province of China
City	Hsinchu
Period	05/4/25 → 05/4/27

ASJC Scopus subject areas

Engineering(all)

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10.1109/VTSA.2005.1497094

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Kubicek, S., Veloso, A., Anil, K. G., Hayashi, S., Yamamoto, K., Mitsuhashi, R., Kittl, A., Lauwers, M., Van Dal, S., Horii, Harada, Y., Kubota, M., Niwa, M., De Gendt, S., Heyns, M., Jurczak, M., & Biesemans, S. (2005). Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS. In 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers (pp. 99-100). [T63] (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). https://doi.org/10.1109/VTSA.2005.1497094

Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS. / Kubicek, S.; Veloso, A.; Anil, K. G.; Hayashi, S.; Yamamoto, K.; Mitsuhashi, R.; Kittl, A.; Lauwers, M.; Van Dal, S.; Horii; Harada, Y.; Kubota, M.; Niwa, M.; De Gendt, S.; Heyns, M.; Jurczak, M.; Biesemans, S.

2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 99-100 T63 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kubicek, S, Veloso, A, Anil, KG, Hayashi, S, Yamamoto, K, Mitsuhashi, R, Kittl, A, Lauwers, M, Van Dal, S, Horii, Harada, Y, Kubota, M, Niwa, M, De Gendt, S, Heyns, M, Jurczak, M & Biesemans, S 2005, Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS. in 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers., T63, 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, pp. 99-100, 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Hsinchu, Taiwan, Province of China, 05/4/25. https://doi.org/10.1109/VTSA.2005.1497094

Kubicek S, Veloso A, Anil KG, Hayashi S, Yamamoto K, Mitsuhashi R et al. Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS. In 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 99-100. T63. (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). https://doi.org/10.1109/VTSA.2005.1497094

Kubicek, S. ; Veloso, A. ; Anil, K. G. ; Hayashi, S. ; Yamamoto, K. ; Mitsuhashi, R. ; Kittl, A. ; Lauwers, M. ; Van Dal, S. ; Horii ; Harada, Y. ; Kubota, M. ; Niwa, M. ; De Gendt, S. ; Heyns, M. ; Jurczak, M. ; Biesemans, S. / Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS. 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. pp. 99-100 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

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abstract = "We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like Cinv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the VDD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.",

author = "S. Kubicek and A. Veloso and Anil, {K. G.} and S. Hayashi and K. Yamamoto and R. Mitsuhashi and A. Kittl and M. Lauwers and {Van Dal}, S. and Horii and Y. Harada and M. Kubota and M. Niwa and {De Gendt}, S. and M. Heyns and M. Jurczak and S. Biesemans",

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AU - Kubicek, S.

AU - Veloso, A.

AU - Anil, K. G.

AU - Hayashi, S.

AU - Yamamoto, K.

AU - Mitsuhashi, R.

AU - Kittl, A.

AU - Lauwers, M.

AU - Van Dal, S.

AU - Horii,

AU - Harada, Y.

AU - Kubota, M.

AU - Niwa, M.

AU - De Gendt, S.

AU - Heyns, M.

AU - Jurczak, M.

AU - Biesemans, S.

PY - 2005/10/31

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N2 - We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like Cinv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the VDD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.

AB - We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like Cinv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the VDD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.

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