TY - GEN
T1 - Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS
AU - Kubicek, S.
AU - Veloso, A.
AU - Anil, K. G.
AU - Hayashi, S.
AU - Yamamoto, K.
AU - Mitsuhashi, R.
AU - Kittl, A.
AU - Lauwers, M.
AU - Van Dal, S.
AU - Horii,
AU - Harada, Y.
AU - Kubota, M.
AU - Niwa, M.
AU - De Gendt, S.
AU - Heyns, M.
AU - Jurczak, M.
AU - Biesemans, S.
PY - 2005/10/31
Y1 - 2005/10/31
N2 - We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like Cinv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the VDD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.
AB - We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like Cinv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the VDD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.
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U2 - 10.1109/VTSA.2005.1497094
DO - 10.1109/VTSA.2005.1497094
M3 - Conference contribution
AN - SCOPUS:27144544089
SN - 078039058X
SN - 9780780390584
T3 - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers
SP - 99
EP - 100
BT - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
T2 - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
Y2 - 25 April 2005 through 27 April 2005
ER -