Ni-FUSI on high-k as a candidate for 65nm LSTP CMOS

S. Kubicek, A. Veloso, K. G. Anil, S. Hayashi, K. Yamamoto, R. Mitsuhashi, A. Kittl, M. Lauwers, S. Van Dal, Horii, Y. Harada, M. Kubota, M. Niwa, S. De Gendt, M. Heyns, M. Jurczak, S. Biesemans

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We show for the first time that full Ni silicidation (Ni-FUSI) of poly gates in combination with Hf based gate dielectrics meets the required device performance for the 65nm LSTP technology node. Important device parameters, like Cinv, mobility and drive currents exhibit significant improvement without compromising the oxide integrity and reliability. The drive of nMOS and pMOS transistors for the VDD=1.1V at 10pA/μm off state leakage is 575μA/ μm and 1650 μA/μm respectively.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
Pages99-100
Number of pages2
DOIs
Publication statusPublished - 2005 Oct 31
Externally publishedYes
Event2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan, Province of China
Duration: 2005 Apr 252005 Apr 27

Publication series

Name2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Other

Other2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
CountryTaiwan, Province of China
CityHsinchu
Period05/4/2505/4/27

ASJC Scopus subject areas

  • Engineering(all)

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