New write/erase method for the reduction of the stress-induced leakage current based on the deactivation of step tunneling sites for flash memories

T. Endoh, K. Shimizu, H. Iizuka, S. Watanabe, F. Masuoka

Research output: Contribution to journalConference articlepeer-review

5 Citations (Scopus)

Abstract

This paper describes a new write/erase method to improve the read disturb characteristics by means of drastically reducing the stress-induced leakage current in the tunnel oxide. With the proposed write/erase method, the degradation of the read disturb life time after 106 write/erase cycles can be drastically reduced to 50% in comparison with the conventional bipolarity write/erase method. The features of the proposed write/erase method are as follows: (1) applying an additional pulse to the control gate just after a completion of the write/erase operation, (2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower enough than that of a control gate in a write operation. (3) the polarity of the voltage is the same as that of the control gate voltage in the read operation. This proposed write/erase method is based on the deactivation mechanism of the leakage current, which will be discussed in detail in this paper.

Original languageEnglish
Pages (from-to)49-52
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1994 Dec 1
Externally publishedYes
EventProceedings of the 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1994 Dec 111994 Dec 14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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