New wafer stacking technology for three-dimensional sysytem-on-a chip

H. Kurino, T. Nakamura, K. W. Lee, Y. Igarashi, T. Mizukusa, Y. Yamada, T. Morooka, M. Koyanagi

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

We propose a new wafer stacking technology to integrate various kinds of devices into three-dimensional (3D) SoC. In 3D SoC, each circuit layer is stacked and electrically connected vertically using a huge number of buried interconnections and micro bumps. Hence we can dramatically increase the wiring connectivity and reduce the long wirings and integrate various kinds of devices with different fabrication process sequences into one chip. In this paper, we fabricated a 3D microprocessor consisting of three circuit layers and demonstrated the basic operation of the 3D microporcessor.

Original languageEnglish
Pages (from-to)137-142
Number of pages6
JournalAdvanced Metallization Conference (AMC)
Publication statusPublished - 2001 Dec 1
EventAdvanced Metallization Conference 2001 (AMC 2001) - Montreal, Que., Canada
Duration: 2001 Oct 82001 Oct 11

ASJC Scopus subject areas

  • Chemical Engineering(all)

Fingerprint Dive into the research topics of 'New wafer stacking technology for three-dimensional sysytem-on-a chip'. Together they form a unique fingerprint.

Cite this