TY - JOUR
T1 - New wafer stacking technology for three-dimensional sysytem-on-a chip
AU - Kurino, H.
AU - Nakamura, T.
AU - Lee, K. W.
AU - Igarashi, Y.
AU - Mizukusa, T.
AU - Yamada, Y.
AU - Morooka, T.
AU - Koyanagi, M.
PY - 2001/12/1
Y1 - 2001/12/1
N2 - We propose a new wafer stacking technology to integrate various kinds of devices into three-dimensional (3D) SoC. In 3D SoC, each circuit layer is stacked and electrically connected vertically using a huge number of buried interconnections and micro bumps. Hence we can dramatically increase the wiring connectivity and reduce the long wirings and integrate various kinds of devices with different fabrication process sequences into one chip. In this paper, we fabricated a 3D microprocessor consisting of three circuit layers and demonstrated the basic operation of the 3D microporcessor.
AB - We propose a new wafer stacking technology to integrate various kinds of devices into three-dimensional (3D) SoC. In 3D SoC, each circuit layer is stacked and electrically connected vertically using a huge number of buried interconnections and micro bumps. Hence we can dramatically increase the wiring connectivity and reduce the long wirings and integrate various kinds of devices with different fabrication process sequences into one chip. In this paper, we fabricated a 3D microprocessor consisting of three circuit layers and demonstrated the basic operation of the 3D microporcessor.
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M3 - Conference article
AN - SCOPUS:0035555360
SP - 137
EP - 142
JO - Advanced Metallization Conference (AMC)
JF - Advanced Metallization Conference (AMC)
SN - 1540-1766
T2 - Advanced Metallization Conference 2001 (AMC 2001)
Y2 - 8 October 2001 through 11 October 2001
ER -