New three-dimensional integration technology using self-assembly technique

Takafumi Fukushima, Yusuke Yamada, Hirokazu Kikuchi, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

64 Citations (Scopus)

Abstract

To achieve ultimate super chip integration, we have developed a new three-dimensional integration technology called Super-Smart-Stack technology using a novel self-assembly technique. The chip alignment accuracy of within 1μm is obtained by the self-assembly technique. We demonstrated for the first time that 3D SRAM test chip with ten memory layers was successfully fabricated using the Super-Smart-Stack (SSS) technology.

Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages348-351
Number of pages4
Publication statusPublished - 2005 Dec 1
EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
Duration: 2005 Dec 52005 Dec 7

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2005
ISSN (Print)0163-1918

Other

OtherIEEE International Electron Devices Meeting, 2005 IEDM
Country/TerritoryUnited States
CityWashington, DC, MD
Period05/12/505/12/7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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