TY - GEN
T1 - New three-dimensional integration technology using reconfigured wafers
AU - Koyanagi, Mitsumasa
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
PY - 2008
Y1 - 2008
N2 - We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).
AB - We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).
UR - http://www.scopus.com/inward/record.url?scp=60649087195&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=60649087195&partnerID=8YFLogxK
U2 - 10.1109/ICSICT.2008.4734759
DO - 10.1109/ICSICT.2008.4734759
M3 - Conference contribution
AN - SCOPUS:60649087195
SN - 9781424421855
T3 - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
SP - 1188
EP - 1191
BT - ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
T2 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
Y2 - 20 October 2008 through 23 October 2008
ER -