New three-dimensional integration technology using reconfigured wafers

Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka

doi:10.1109/ICSICT.2008.4734759

New three-dimensional integration technology using reconfigured wafers

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).

Original language	English
Title of host publication	ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages	1188-1191
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2008.4734759
Publication status	Published - 2008 Dec 1
Event	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China Duration: 2008 Oct 20 → 2008 Oct 23

Publication series

Name	International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Other

Other	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
Country	China
City	Beijing
Period	08/10/20 → 08/10/23

ASJC Scopus subject areas

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ICSICT.2008.4734759

Fingerprint Dive into the research topics of 'New three-dimensional integration technology using reconfigured wafers'. Together they form a unique fingerprint.

Cite this

Koyanagi, M., Fukushima, T., & Tanaka, T. (2008). New three-dimensional integration technology using reconfigured wafers. In ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings (pp. 1188-1191). [4734759] (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT). https://doi.org/10.1109/ICSICT.2008.4734759

New three-dimensional integration technology using reconfigured wafers. / Koyanagi, Mitsumasa; Fukushima, Takafumi ; Tanaka, Tetsu.

ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 1188-1191 4734759 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Koyanagi, M, Fukushima, T & Tanaka, T 2008, New three-dimensional integration technology using reconfigured wafers. in ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings., 4734759, International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, pp. 1188-1191, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, Beijing, China, 08/10/20. https://doi.org/10.1109/ICSICT.2008.4734759

Koyanagi M, Fukushima T , Tanaka T. New three-dimensional integration technology using reconfigured wafers. In ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 1188-1191. 4734759. (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT). https://doi.org/10.1109/ICSICT.2008.4734759

@inproceedings{8a65075a681447d49fb9467a55f5f7e3,

title = "New three-dimensional integration technology using reconfigured wafers",

abstract = "We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).",

author = "Mitsumasa Koyanagi and Takafumi Fukushima and Tetsu Tanaka",

year = "2008",

month = dec,

day = "1",

doi = "10.1109/ICSICT.2008.4734759",

language = "English",

isbn = "9781424421855",

series = "International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT",

pages = "1188--1191",

booktitle = "ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings",

note = "2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 ; Conference date: 20-10-2008 Through 23-10-2008",

}

TY - GEN

T1 - New three-dimensional integration technology using reconfigured wafers

AU - Koyanagi, Mitsumasa

AU - Fukushima, Takafumi

AU - Tanaka, Tetsu

PY - 2008/12/1

Y1 - 2008/12/1

N2 - We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).

AB - We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).

UR - http://www.scopus.com/inward/record.url?scp=60649087195&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=60649087195&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2008.4734759

DO - 10.1109/ICSICT.2008.4734759

M3 - Conference contribution

AN - SCOPUS:60649087195

SN - 9781424421855

T3 - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

SP - 1188

EP - 1191

BT - ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings

T2 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

Y2 - 20 October 2008 through 23 October 2008

ER -