Abstract
A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In-Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7mm2 and ranging in thickness from 30 to 90 μm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.
| Original language | English |
|---|---|
| Pages (from-to) | 3030-3035 |
| Number of pages | 6 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 45 |
| Issue number | 4 B |
| DOIs | |
| Publication status | Published - 2006 Apr 25 |
Keywords
- Adhesive injection
- Chemical mechanical polishing
- Chip alignment
- Chip-to-wafer bonding
- Deep Si etching
- Known good dies
- Super-chip integration
- Three-dimensional integration technology
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)