New three dimensional (3D) memory array architecture for future ultra high density DRAM

T. Endoh, H. Sakuraba, K. Shinmei, F. Masuoka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM, when one bit-line has 1K-bit cells and the same design rules are used. Moreover, array area of 1M-bit DRAM using the proposed architecture, is reduced to 11.5% of normal DRAM using the same design rules.

Original languageEnglish
Title of host publication2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
PublisherIEEE
Pages447-450
Number of pages4
ISBN (Print)0780352351, 9780780352353
Publication statusPublished - 1999 Jan 1
Event22nd International Conference on Microelectronics (MIEL 2000) - Nis, Yugoslavia
Duration: 2000 May 142000 May 17

Publication series

Name2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
Volume2

Other

Other22nd International Conference on Microelectronics (MIEL 2000)
CityNis, Yugoslavia
Period00/5/1400/5/17

ASJC Scopus subject areas

  • Engineering(all)

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