New three dimensional (3D) memory array architecture for future ultra high density DRAM (invited)

F. Masuoka, Tetsuo Endoh, H. Sakuraba

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

Three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in a two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of that of a normal DRAM, when one bit-line has 1K-bit cells and the same design rules are used. Moreover, array area of a 1 Mbit DRAM using the proposed architecture, is reduced to 11.5% of that of a normal DRAM using the same design rules.

Original languageEnglish
DOIs
Publication statusPublished - 2002 Jan 1
Event4th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS 2002 - Oranjestad, Aruba, Netherlands
Duration: 2002 Apr 172002 Apr 19

Other

Other4th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS 2002
CountryNetherlands
CityOranjestad, Aruba
Period02/4/1702/4/19

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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