New multichip-to-wafer 3D integration technology using Self-Assembly and Cu nano-pillar hybrid bonding

Mitsumasa Koyanagi, Kanuku Ri, T. Fukushima, T. Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

New 3D integration technology using self-assembly and Cu nano-pillar hybrid bonding are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled with a high alignment accuracy making use of liquid surface tension in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier and electrostatically bonded by applying a voltage to bipolar electrodes on the SAE carrier. The self-assembled dies on the carrier are simultaneously transferred to another wafer or interposer wafer by electrostatically debonding the carrier wafer after Cu nano-pillar hybrid bonding of self-assembled dies.

Original languageEnglish
Title of host publication2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings
EditorsRu Huang, Ting-Ao Tang, Yu-Long Jiang
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages338-341
Number of pages4
ISBN (Electronic)9781467397179
DOIs
Publication statusPublished - 2016 Jan 1
Event13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Hangzhou, China
Duration: 2016 Oct 252016 Oct 28

Publication series

Name2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings

Other

Other13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016
CountryChina
CityHangzhou
Period16/10/2516/10/28

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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