New findings in nano-scale interface physics and their relations to nano-CMOS technologies

K. Shiraishi, Y. Akasaka, K. Torii, T. Nakayama, S. Miyazaki, T. Nakaoka, H. Watanabe, K. Ohmori, P. Ahmet, T. Chikyow, Y. Nara, K. Yamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We show the new findings in nano-scale interface physics and atomistic beheviors of defects in gate dielectric materials. In this paper, we first discuss the relation between defect behaviors and transistor characteristics. Next, we introduce our newly prosed mechanism of Fermi level pinning governed by the interface reaction. Further, we show that conventional charge neutrality level concept does not applicable to metal/high-k dielectric interfaces, and we propose a generalized charge neutrality level concept that includes both nano-scale interface structures and metal band structures. Finally, we discuss the atomistic investigation on the characteristics of conventional Si/SiO2 nemo interfaces

Original languageEnglish
Title of host publication1st IEEE International Workshop on Nano CMOS, IEEE IWNC 2006
Pages180-208
Number of pages29
DOIs
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event1st IEEE International Workshop on Nano CMOS, IEEE IWNC 2006 - Mishima, Shizuoka, Japan
Duration: 2006 Jan 302006 Feb 1

Publication series

Name2006 International Workshop on Nano CMOS - Proceedings, IWNC

Other

Other1st IEEE International Workshop on Nano CMOS, IEEE IWNC 2006
CountryJapan
CityMishima, Shizuoka
Period06/1/3006/2/1

Keywords

  • Defect
  • Effective work functions
  • Fermi level pinnig
  • High-k dielectrics
  • Inteface
  • Reliability
  • Si
  • SiO
  • Theory

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Shiraishi, K., Akasaka, Y., Torii, K., Nakayama, T., Miyazaki, S., Nakaoka, T., Watanabe, H., Ohmori, K., Ahmet, P., Chikyow, T., Nara, Y., & Yamada, K. (2006). New findings in nano-scale interface physics and their relations to nano-CMOS technologies. In 1st IEEE International Workshop on Nano CMOS, IEEE IWNC 2006 (pp. 180-208). [4570992] (2006 International Workshop on Nano CMOS - Proceedings, IWNC). https://doi.org/10.1109/IWNC.2006.4570992