New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

M. Momodomi, R. Kirisawa, R. Nakayama, S. Aritome, T. Endoh, Y. Itoh, Y. Iwata, H. Oodaira, T. Tanaka, M. Chiba, R. Shirota, F. Masuoka

Research output: Contribution to journalConference articlepeer-review

18 Citations (Scopus)

Abstract

Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0-μm design rules, the unit cell area per bit is 12.9 μm2, which is small enough to realize a 4-Mb EEPROM.

Original languageEnglish
Pages (from-to)412-415
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1988 Dec 1
Externally publishedYes
EventTechnical Digest - International Electron Devices Meeting 1988 - San Francisco, CA, USA
Duration: 1988 Dec 111988 Dec 14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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