New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

M. Momodomi; R. Kirisawa; R. Nakayama; S. Aritome; T. Endoh; Y. Itoh; Y. Iwata; H. Oodaira; T. Tanaka; M. Chiba; R. Shirota; F. Masuoka

New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

M. Momodomi, R. Kirisawa, R. Nakayama, S. Aritome, T. Endoh, Y. Itoh, Y. Iwata, H. Oodaira, T. Tanaka, M. Chiba, R. Shirota, F. Masuoka

Research output: Contribution to journal › Conference article › peer-review

19 Citations (Scopus)

Abstract

Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0-μm design rules, the unit cell area per bit is 12.9 μm², which is small enough to realize a 4-Mb EEPROM.

Original language	English
Pages (from-to)	412-415
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1988 Dec 1
Externally published	Yes
Event	Technical Digest - International Electron Devices Meeting 1988 - San Francisco, CA, USA Duration: 1988 Dec 11 → 1988 Dec 14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell. / Momodomi, M.; Kirisawa, R.; Nakayama, R.; Aritome, S.; Endoh, T.; Itoh, Y.; Iwata, Y.; Oodaira, H.; Tanaka, T.; Chiba, M.; Shirota, R.; Masuoka, F.

In: Technical Digest - International Electron Devices Meeting, 01.12.1988, p. 412-415.

Research output: Contribution to journal › Conference article › peer-review

@article{087e046e436448968eb02bdfa13f5284,

title = "New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell",

abstract = "Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0-μm design rules, the unit cell area per bit is 12.9 μm2, which is small enough to realize a 4-Mb EEPROM.",

author = "M. Momodomi and R. Kirisawa and R. Nakayama and S. Aritome and T. Endoh and Y. Itoh and Y. Iwata and H. Oodaira and T. Tanaka and M. Chiba and R. Shirota and F. Masuoka",

year = "1988",

month = dec,

day = "1",

language = "English",

pages = "412--415",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Technical Digest - International Electron Devices Meeting 1988 ; Conference date: 11-12-1988 Through 14-12-1988",

}

TY - JOUR

T1 - New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

AU - Momodomi, M.

AU - Kirisawa, R.

AU - Nakayama, R.

AU - Aritome, S.

AU - Endoh, T.

AU - Itoh, Y.

AU - Iwata, Y.

AU - Oodaira, H.

AU - Tanaka, T.

AU - Chiba, M.

AU - Shirota, R.

AU - Masuoka, F.

PY - 1988/12/1

Y1 - 1988/12/1

N2 - Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0-μm design rules, the unit cell area per bit is 12.9 μm2, which is small enough to realize a 4-Mb EEPROM.

AB - Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0-μm design rules, the unit cell area per bit is 12.9 μm2, which is small enough to realize a 4-Mb EEPROM.

UR - http://www.scopus.com/inward/record.url?scp=0024176887&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024176887&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0024176887

SP - 412

EP - 415

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

T2 - Technical Digest - International Electron Devices Meeting 1988

Y2 - 11 December 1988 through 14 December 1988

ER -

New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

Abstract

ASJC Scopus subject areas

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