New design technology for EEPROM memory cells with 10 million write/erase cycling endurance

T. Endoh, R. Shirota, Y. Tanaka, R. Nakayama, R. Kirisawa, S. Aritome, F. Masuoka

Research output: Contribution to journalConference articlepeer-review

5 Citations (Scopus)


The authors describe a novel design technology for improving the write/erase cycling endurance characteristics for EEPROM (electrically erasable programmable ROM) memory cells with self-aligned double polycrystalline silicon stacked structure. In this device, the source n+ region is located within the depletion region of the surface channel area when high voltage is applied to the drain with the source left floating. It is confirmed experimentally that the endurance of the newly designed memory cell using an 0.5-μm design rule can be more than 107 write/erase cycles. This memory cell has superior potential for application to 64-Mb flash or 4-Mb full-featured EEPROMs.

Original languageEnglish
Pages (from-to)599-602
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1989 Jan 1
Externally publishedYes
Event1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA
Duration: 1989 Dec 31989 Dec 6

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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