A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.
|Number of pages||2|
|Publication status||Published - 1988 Dec 1|
|Event||1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan|
Duration: 1988 Aug 22 → 1988 Aug 24
|Other||1988 Symposium on VLSI Circuits - Digest of Technical Papers|
|Period||88/8/22 → 88/8/24|
ASJC Scopus subject areas