New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

T. Fukushima, H. Hashiguchi, J. Bea, Y. Ohara, M. Murugesan, K. W. Lee, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of < 1 μm. The electrostatic multichip temporary bonding technique enabled stress-free direct bonding of self-assembled chips. We obtained good electrical characteristics from 3D stacked chips fabricated by HSA-CtW using Cu/SnAg microbumps and Cu-TSVs.

Original languageEnglish
Title of host publication2012 IEEE International Electron Devices Meeting, IEDM 2012
Pages33.3.1-33.3.4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States
Duration: 2012 Dec 102012 Dec 13

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2012 IEEE International Electron Devices Meeting, IEDM 2012
CountryUnited States
CitySan Francisco, CA
Period12/12/1012/12/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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