New 3D integration technology and 3D system LSIs

Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding has been developed. Various kinds of 3-D LSI test chips such as 3-D microprocessor chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology called super-chip integration based on the reconfigured wafer- to-wafer bonding in which the reconfigured wafers are produced by simultaneously aligning and bonding more than one thousand of known good dies (KGD's) on a supporting wafer using a self-assembly technique.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages64-67
Number of pages4
Publication statusPublished - 2009 Nov 16
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period09/6/1609/6/18

Keywords

  • 3D LSI
  • Super chip
  • TSV
  • Wafer bonding

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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