TY - JOUR
T1 - Neuron-Synapse IC Chip-Set for Large-Scale Chaotic Neural Networks
AU - Horio, Yoshihiko
AU - Aihara, Kazuyuki
AU - Yamamoto, O.
N1 - Funding Information:
Manuscript received July 22, 2002; revised February 25, 2003. This work was supported by CREST, JST. Y. Horio and O. Yamamoto are with the Department of Electronic Engineering, Tokyo Denki University, Tokyo 101-8457, Japan (e-mail: horio@d.dendai.ac.jp). K. Aihara is with the Department of Complexity Science and Engineering, Graduate School of Frontier Sciences, University of Tokyo, Tokyo 113-8656, Japan. Digital Object Identifier 10.1109/TNN.2003.816349
PY - 2003/9
Y1 - 2003/9
N2 - We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real numbers through continuous state variables of the analog circuitry. We can digitally control most of the model parameters by means of programmable capacitive arrays embedded in the SC chaotic neuron chip. Since the output of the neuron is transfered into a digital pulse according to the all-or-nothing property of an axon, we design a synapse chip with digital circuits. We propose a memory-based synapse circuit architecture to achieve a rapid calculation of a vast number of weighted summations. Both of the SC neuron and the digital synapse circuits have been fabricated as IC forms. We have tested these IC chips extensively, and confirmed the functions and performance of the chip-set. The proposed neuron-synapse IC chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10000 neurons and 10 0002 synaptic connections.
AB - We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real numbers through continuous state variables of the analog circuitry. We can digitally control most of the model parameters by means of programmable capacitive arrays embedded in the SC chaotic neuron chip. Since the output of the neuron is transfered into a digital pulse according to the all-or-nothing property of an axon, we design a synapse chip with digital circuits. We propose a memory-based synapse circuit architecture to achieve a rapid calculation of a vast number of weighted summations. Both of the SC neuron and the digital synapse circuits have been fabricated as IC forms. We have tested these IC chips extensively, and confirmed the functions and performance of the chip-set. The proposed neuron-synapse IC chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10000 neurons and 10 0002 synaptic connections.
KW - Chaos
KW - Chaotic neural networks
KW - Large-scale neural networks
KW - Mixed analog/digital system
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U2 - 10.1109/TNN.2003.816349
DO - 10.1109/TNN.2003.816349
M3 - Article
C2 - 18244585
AN - SCOPUS:0141757101
SN - 2162-237X
VL - 14
SP - 1393
EP - 1404
JO - IEEE Transactions on Neural Networks and Learning Systems
JF - IEEE Transactions on Neural Networks and Learning Systems
IS - 5
ER -