Abstract
The nanoscale wet etching of physical-vapor-deposited (PVD) titanium nitride (TiN) and its application to sub-30-nm-gate-length fin-type doublegate metal-oxide-semiconductor field-effect transistor (FinFET) fabrication are systematically investigated. It is experimentally found that PVDTiN side-etching depth can be controlled to be one-half of PVD-TiN thickness with precise time control using an ammonium hydroxide (NH4OH) : hydrogen peroxide (H2O2) : deionized water (H2O) = 1 : 2 : 5 solution at 60 °C. Using the developed nanoscale PVD-TiN wet etching technique, sub-30-nm-physical-gate-length FinFETs, 100-nm-tall fin-channel complementary MOS (CMOS) inverters and static random access memory (SRAM) half-cells have successfully been fabricated and demonstrated. These experimental results indicate that the developed nanoscale PVDTiN wet etching technique is very useful for tall fin-channel CMOS fabrication.
Original language | English |
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Pages (from-to) | 06GH181-06GH185 |
Journal | Japanese journal of applied physics |
Volume | 49 |
Issue number | 6 PART 2 |
DOIs | |
Publication status | Published - 2010 Jun |
Externally published | Yes |
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)