Nanoscale TiN wet etching and its application for FinFET fabrication

Y. X. Liu, T. Kamei, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, T. Hayashida, Y. Ishikawa, T. Matsukawa, K. Sakamoto, A. Ogura, M. Masahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The nanoscale TiN wet etching and its application for FinFET fabrication have been systematically investigated. It is experimentally found that the TiN side-etching can be controlled to be half of TiN thickness with precise time control. By using the developed nanoscale TiN wet etching technique, sub-30-nm physical gate length FinFETs, 100-nm tall fin CMOS inverters and SRAM half-cells have successfully been fabricated. These experimental results indicate that the developed nanoscale TiN wet etching technique is very useful for the tall fin CMOS fabrication.

Original languageEnglish
Title of host publication2009 International Semiconductor Device Research Symposium, ISDRS '09
DOIs
Publication statusPublished - 2009 Dec 1
Externally publishedYes
Event2009 International Semiconductor Device Research Symposium, ISDRS '09 - College Park, MD, United States
Duration: 2009 Dec 92009 Dec 11

Publication series

Name2009 International Semiconductor Device Research Symposium, ISDRS '09

Other

Other2009 International Semiconductor Device Research Symposium, ISDRS '09
CountryUnited States
CityCollege Park, MD
Period09/12/909/12/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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