Nanoscale Coulomb blockade memory and logic devices

Hiroshi Mizuta, Heinz Olaf Müller, Kazuhito Tsukagoshi, David Williams, Zahid Durrani, Andrew Irvine, Gareth Evans, Shuhei Amakawa, Kazuo Nakazato, Haroon Ahmed

Research output: Contribution to journalConference articlepeer-review

20 Citations (Scopus)

Abstract

This paper gives a brief review of our recent work done in the area of nanometre-scale Coulomb blockade (CB) memory and logic devices, that enable us to realize future electron-number scalability by overcoming inherent problems to conventional semiconductor devices. We introduce multiple-tunnel junctions (MTJs), naturally formed in heavily doped semiconductor nanowires, as a key building block for our CB devices. For memory applications, the hybrid MTJ/MOS cell architecture is described, and its high-speed RAM operation is investigated. For logic applications the binary decision diagram logic is discussed as a suitable architecture for low-gain MTJ transistors.

Original languageEnglish
Pages (from-to)155-159
Number of pages5
JournalNanotechnology
Volume12
Issue number2
DOIs
Publication statusPublished - 2001 Jun
Externally publishedYes
EventTrends in Nanotechnology (TNT 2000) Conference - Toledo, Spain
Duration: 2000 Oct 122000 Oct 16

ASJC Scopus subject areas

  • Bioengineering
  • Chemistry(all)
  • Materials Science(all)
  • Mechanics of Materials
  • Mechanical Engineering
  • Electrical and Electronic Engineering

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