Nanoscale capacitance-voltage profiling of DC bias induced stress on a high-κ/SiO2/Si gate stack

Koharu Suzuki, Kohei Yamasue, Yasuo Cho

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


We investigate DC bias stress effects on a HfOx/SiO2/p-Si gate stack using time-resolved scanning nonlinear dielectric microscopy. Our microscopy permits localized capacitance-voltage profiling and deep level transient spectroscopy on a particular area stressed prior to the measurement. We observed the increase of interface defect density and the drastic changes of local capacitance-voltage characteristics on the stressed area. Our numerical simulations explain that both fixed charges and interface defect density increased by the DC bias stress and caused the change of local characteristics. Because local capacitance-voltage characteristics is particularly important in device performance, time-resolved scanning nonlinear dielectric microscopy will be useful for the evaluation of local stress effects on miniaturized Si devices such as bias temperature instability.

Original languageEnglish
Article number114278
JournalMicroelectronics Reliability
Publication statusPublished - 2021 Nov


  • Bias temperature instability
  • Device reliability
  • Interface
  • Scanning nonlinear dielectric microscopy
  • Scanning prove microscopy
  • Silicon

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


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