## Abstract

This paper proposes a new parallel multiplier based on the redundant number representation using positive digits (called redundant positive‐digit number representation, or simply PD number representation). The proposed algorithm is the fastest algorithm that can execute the multiplication of n x n digit by a time proportional to log_{2}n. The structure is regular and is suited to LSI implementation. The proposed parallel multiplier is designed in two ways, i.e., by the multivated current mode circuit and by the binary digital circuit. Then the results are evaluated. The circuit designed by the multivated current mode, especially, has the feature that the 6‐input addition with partial product operand can be executed by the wired addition and a single‐stage parallel adder based on the PD number representation. Thus, it is demonstrated that the circuit has a high speed and can be realized with a very small number of elements and wirings. The basic circuits for the proposed parallel multiplier are constructed experimentally by 5 μm CMOS technology, and a satisfactory performance is verified.

Original language | English |
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Pages (from-to) | 40-52 |

Number of pages | 13 |

Journal | Systems and Computers in Japan |

Volume | 24 |

Issue number | 5 |

DOIs | |

Publication status | Published - 1993 |

## Keywords

- Parallel multiplier
- current‐mode circuit
- multiple‐valued logic
- redundant number representation

## ASJC Scopus subject areas

- Theoretical Computer Science
- Information Systems
- Hardware and Architecture
- Computational Theory and Mathematics