Multiplier block synthesis using evolutionary graph generation

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a graph-based evolutionary optimization technique, called Evolutionary Graph Generation (EGG), and its application to hierarchical synthesis of arithmetic circuits. In stead of creating bit-level circuits directly, the EGG system generates arithmetic data-flow graphs that can be transformed into actual bit-level circuit configurations. The potential capability of EGG has been investigated through an experiment of synthesizing multiplier blocks which are used in many DSP applications.

Original languageEnglish
Title of host publicationProceedings - 2004 NASA/DoD Conference on Evolvable Hardware
EditorsR.S. Zebulum, D. Gwaltney, G. Hornby, D. Keymeulen, J. Lohn, A. Stoica
Pages79-82
Number of pages4
DOIs
Publication statusPublished - 2004 Dec 1
EventProceedings - 2004 NASA/DoD Conference on Evolvable Hardware - Seattle, WA, United States
Duration: 2004 Jun 242004 Jun 26

Publication series

NameProceedings - 2004 NASA/DoD Conference on Evolvable Hardware

Other

OtherProceedings - 2004 NASA/DoD Conference on Evolvable Hardware
CountryUnited States
CitySeattle, WA
Period04/6/2404/6/26

ASJC Scopus subject areas

  • Engineering(all)

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    Homma, N., Aoki, T., & Higuchi, T. (2004). Multiplier block synthesis using evolutionary graph generation. In R. S. Zebulum, D. Gwaltney, G. Hornby, D. Keymeulen, J. Lohn, & A. Stoica (Eds.), Proceedings - 2004 NASA/DoD Conference on Evolvable Hardware (pp. 79-82). (Proceedings - 2004 NASA/DoD Conference on Evolvable Hardware). https://doi.org/10.1109/EH.2004.1310812