Multiple-valued VLSI architecture for intra-chip packet data transfer

Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)


A packet data transfer scheme is introduced for intra-chip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.

Original languageEnglish
Pages (from-to)114-119
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2005 Sep 20
Event35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada
Duration: 2005 May 192005 May 21

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)


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