Multiple-Valued reconfigurable VLSI processor based on superposition of data and control signals

Nobuaki Okada, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A multiple-valued reconfigurable VLSI useful for improving the utilization ratio of hardware resources is proposed. Hybrid architecture based on wired programming and dynamic data-path control can be effectively employed for high utilization ratio of hardware resources with small overhead of additional hardware resources. A 2-to-l multiplexer is provided in each cell. Accordingly, distributed control can be realized simply, so that interconnections between arithmetic logic modules and controllers become very short. Moreover, superposition of data and control signals is introduced to reduce not only complexity of interconnections but also switch block area.

Original languageEnglish
Title of host publicationProceedings - 39th International Symposium on Multiple-Valued Logic, ISMVL 2009
Pages54-59
Number of pages6
DOIs
Publication statusPublished - 2009 Sep 30
Event39th International Symposium on Multiple-Valued Logic, ISMVL 2009 - Naha, Okinawa, Japan
Duration: 2009 May 212009 May 23

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other39th International Symposium on Multiple-Valued Logic, ISMVL 2009
CountryJapan
CityNaha, Okinawa
Period09/5/2109/5/23

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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