This paper presents a multiple-valued multiple-rail encoding scheme for low-power asynchronous data transfer between modules inside a VLSI chip. The use of multiple-rail encoding makes it possible to reduce the dynamic range in a single wire. If signal levels per wire are reduced, the asynchronous data transfer between modules can be performed more efficiently with maintained data-transfer capability. Some appropriate combinations of signal levels per wire and wire counts for low-power asynchronous communication are presented. It is demonstrated that the power-delay products per value for asynchronous data transfer between modules are evaluated in some cases using the proposed encoding scheme.
|Number of pages||6|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2004 Jul 26|
|Event||Proceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada|
Duration: 2004 May 19 → 2004 May 22
ASJC Scopus subject areas
- Computer Science(all)