Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits

Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

This paper presents a compact multiple-valued mask-programmable logic array (MPLA) based on a MIN/TSUM (MINimum/Truncated-SUM) two-level synthesis. A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MIN plane. Since a threshold literal can be designed by using a single floating-gate MOS transistor, a compact MIN plane can be implemented in the proposed MPLA. Any arbitrary universal-literal circuits can be realized by programming the threshold voltage of the corresponding floating-gate MOS transistor and selecting an appropriate LVC as an input variable. The performance of the proposed MPLA is evaluated under a 0.8μm CMOS design. It is demonstrated that its performance is superior to that of conventional PLA's.

Original languageEnglish
Pages (from-to)167-172
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
DOIs
Publication statusPublished - 2001 Jan 1

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

Fingerprint Dive into the research topics of 'Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits'. Together they form a unique fingerprint.

Cite this