TY - JOUR
T1 - Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits
AU - Hanyu, Takahiro
AU - Kameyama, Michitaka
AU - Shimabukuro, Katsuhiko
AU - Zukeran, Chotei
PY - 2001/1/1
Y1 - 2001/1/1
N2 - This paper presents a compact multiple-valued mask-programmable logic array (MPLA) based on a MIN/TSUM (MINimum/Truncated-SUM) two-level synthesis. A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MIN plane. Since a threshold literal can be designed by using a single floating-gate MOS transistor, a compact MIN plane can be implemented in the proposed MPLA. Any arbitrary universal-literal circuits can be realized by programming the threshold voltage of the corresponding floating-gate MOS transistor and selecting an appropriate LVC as an input variable. The performance of the proposed MPLA is evaluated under a 0.8μm CMOS design. It is demonstrated that its performance is superior to that of conventional PLA's.
AB - This paper presents a compact multiple-valued mask-programmable logic array (MPLA) based on a MIN/TSUM (MINimum/Truncated-SUM) two-level synthesis. A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MIN plane. Since a threshold literal can be designed by using a single floating-gate MOS transistor, a compact MIN plane can be implemented in the proposed MPLA. Any arbitrary universal-literal circuits can be realized by programming the threshold voltage of the corresponding floating-gate MOS transistor and selecting an appropriate LVC as an input variable. The performance of the proposed MPLA is evaluated under a 0.8μm CMOS design. It is demonstrated that its performance is superior to that of conventional PLA's.
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U2 - 10.1109/ISMVL.2001.924568
DO - 10.1109/ISMVL.2001.924568
M3 - Article
AN - SCOPUS:0034828944
SP - 167
EP - 172
JO - Proceedings of The International Symposium on Multiple-Valued Logic
JF - Proceedings of The International Symposium on Multiple-Valued Logic
SN - 0195-623X
ER -