Multiple-valued logic-in-memory VLSI based on ferroelectric capacitor storage and charge addition

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

A multiple-valued logic-in-memory VLSI using ferroelectric capacitors is proposed to realize an arithmetic-oriented VLSI with real-time programmable capacitor storage. The use of a remnant-polarization charge on a ferroelectric capacitor makes it possible to perform not only a real-time programmable storage function, but also a linear-sum function, thereby resulting in a compact hardware while maintaining a high-speed processing capability. As a design example, a full adder with a storage capability is evaluated. Its performance is superior to that of a corresponding binary CMOS implementation.

Original languageEnglish
Pages (from-to)161-166
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2002 Jan 1
Event32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States
Duration: 2002 May 152002 May 18

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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