Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network

T. Hanyu, K. Teranishi, Michitaka Kameyama

Research output: Contribution to journalConference articlepeer-review

19 Citations (Scopus)


A logic-in-memory structure, in which storage functions are distributed over a logic-circuit plane, is described. This structure is perceived as a solution to the communication bottleneck between memory and logic modules. This logic-in memory VLSI based on floating-gate MOS transistors merges storage and switching functions in a multiple-valued-input and binary output combinational logic circuit that is useful for the realization of parallel arithmetic and logic circuits.

Original languageEnglish
Pages (from-to)194-195, 437
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 1998 Jan 1
EventProceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC - San Francisco, CA, USA
Duration: 1998 Feb 51998 Feb 7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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