Abstract
A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-μm flash EEPROM technology.
Original language | English |
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Pages (from-to) | 1662-1668 |
Number of pages | 7 |
Journal | IEICE Transactions on Electronics |
Volume | E82-C |
Issue number | 9 |
Publication status | Published - 1999 Jan 1 |
Keywords
- Flash EEP-ROM technology
- Floating-gate MOS transistor
- Four-valued full adder
- Logic-in-memory structure
- Manhattan distance
- Pass-transistor network
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering