Multiple-valued fine-grain reconfigurable VLSI using a global tree local X-net network

Xu Bai, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review


A global tree local X-net network (GTLX) is introduced to realize high-performance data transfer in a multiple-valued fine-grain reconfigurable VLSI (MVFG-RVLSI). A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer. Moreover, a logic-in-memory architecture is employed for solving data transfer bottleneck between a block data memory and a cell. A local X-net network is utilized to realize simple interconnections and compact switch blocks for eight-near neighborhood data transfer. Moreover, multiple-valued signaling is utilized to improve the utilization of the Xnet network, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each "X" intersection. To evaluate the MVFG-RVLSI, a fast Fourier transform (FFT) operation is mapped onto a previous MVFG-RVLSI using only the X-net network and the MVFG-RVLSI using the GTLX. As a result, the computation time, the power consumption and the transistor count of the MVFG-RVLSI using the GTLX are reduced by 25%, 36% and 56%, respectively, in comparison with those of the MVFG-RVLSI using only the X-net network.

Original languageEnglish
Pages (from-to)2278-2285
Number of pages8
JournalIEICE Transactions on Information and Systems
Issue number9
Publication statusPublished - 2014 Sep


  • Fine-grain reconfigurable VLSI
  • Global tree local X-net network
  • Logic-in-memory architecture
  • Multiple-valued reconfigurable VLSI

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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