Abstract
A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evaluate logic style makes steady current flow cut off, thereby greatly saving the power dissipation. A combination of SCL and dynamic logic styles makes it possible to reduce the power dissipation while maintaining a high-speed switching capability due to small input-voltage swing with SCL. As a typical example of a high-performance arithmetic circuit, a radix-2 signed-digit adder based on the proposed dynamic SCL is implemented in a 0.18-μm CMOS technology. Its power dissipation is reduced to about 33 percent in comparison with that of the corresponding binary CMOS implementation under the normalized switching delay.
Original language | English |
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Pages (from-to) | 207-212 |
Number of pages | 6 |
Journal | Proceedings of The International Symposium on Multiple-Valued Logic |
Publication status | Published - 2003 Jul 21 |
Externally published | Yes |
Event | Thirty-third International Symposium on Multiple-Valued Logic - Tokyo, Japan Duration: 2003 May 16 → 2003 May 19 |
ASJC Scopus subject areas
- Computer Science(all)
- Mathematics(all)