Multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a design of new multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic. This circuit can be efficiently utilized in implementing high-speed arithmetic VLSI systems. The use of dual-rail source-coupled logic makes it possible to reduce an input voltage swing for a threshold detector, so that the switching delay of the threshold detector can be reduced. This property is suitable for implementing high-speed multiple-valued integrated circuits with low supply voltage. It is demonstrated that the delay of the proposed radix-2 signed-digit(SD) adder based on dual-rail source-coupled logic is reduced to 67 percent in comparison with that of the corresponding binary CMOS implementation.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages19-26
Number of pages8
ISBN (Print)0818656522
Publication statusPublished - 1994 Jan 1
EventProceedings of the 24th International Symposium on Multiple-Valued Logic - Boston, MA, USA
Duration: 1994 May 251994 May 27

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

OtherProceedings of the 24th International Symposium on Multiple-Valued Logic
CityBoston, MA, USA
Period94/5/2594/5/27

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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