This paper presents a design of new multiple-valued current-mode MOS integrated circuits based on dual-rail source-coupled logic. This circuit can be efficiently utilized in implementing high-speed arithmetic VLSI systems. The use of dual-rail source-coupled logic makes it possible to reduce an input voltage swing for a threshold detector, so that the switching delay of the threshold detector can be reduced. This property is suitable for implementing high-speed multiple-valued integrated circuits with low supply voltage. It is demonstrated that the delay of the proposed radix-2 signed-digit(SD) adder based on dual-rail source-coupled logic is reduced to 67 percent in comparison with that of the corresponding binary CMOS implementation.