Multiple-valued constant-power adder and its application to cryptographic processor

Naofumi Homma, Yuichi Baba, Atsushi Miyamoto, Takafumi Aoki

Research output: Contribution to journalArticlepeer-review


This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature ofMV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.

Original languageEnglish
Pages (from-to)2117-2125
Number of pages9
JournalIEICE Transactions on Information and Systems
Issue number8
Publication statusPublished - 2010 Aug


  • Arithmetic circuits
  • Cryptographic processors
  • Multiple-valued logic
  • RSA cryptosystem
  • Side-channel attacks

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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