Multiple-valued code assignment algorithm for VLSI-oriented highly parallel K-ary operation circuits

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for K-ary operations. By the decomposition of a given K-ary operation into unary operations a code assigment algorithm for K-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demostrate the usefulness of the proposed algorithm.