This paper presents a new multiple-valued current-mode MOS integrated circuit for high-speed arithmetic systems with a low supply voltage. The use of a multiple-valued source-coupled logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the switching delay of the circuit can be reduced at a low supply voltage. As an application to arithmetic systems, we demonstrate that a 1.5V-supply 200MHz 54 × 54-bit pipelined multiplier using the proposed circuits can be designed with a 0.8-μm standard CMOS technology.
|Number of pages||6|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 1995 Jan 1|
|Event||Proceedings of the 1995 25th International Symposium on Multiple-Valued Logic - Bloomington, IN, USA|
Duration: 1995 May 23 → 1995 May 25
ASJC Scopus subject areas
- Computer Science(all)