TY - GEN
T1 - Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration
AU - Lee, Sungho
AU - Liang, Rui
AU - Miwa, Yuki
AU - Kino, Hisashi
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
N1 - Funding Information:
This work was supported by JSPS KAKENHI Grant Number JP18H04159.
Publisher Copyright:
© 2019 JSPS 191st Committee on Innovative Interface Bonding Technology.
PY - 2019/5
Y1 - 2019/5
N2 - Impact of temporary bonding conditions and temporary adhesive properties on mechanical stresses in multichip thinning is evaluated for high-yield multichip-to-wafer (MC2W) heterogeneous 3D integration. It turned out that no sidewall covering of chips with a temporary adhesive gives low mechanical stress to the chip edge, leading to less chipping and cracking.
AB - Impact of temporary bonding conditions and temporary adhesive properties on mechanical stresses in multichip thinning is evaluated for high-yield multichip-to-wafer (MC2W) heterogeneous 3D integration. It turned out that no sidewall covering of chips with a temporary adhesive gives low mechanical stress to the chip edge, leading to less chipping and cracking.
UR - http://www.scopus.com/inward/record.url?scp=85068373231&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85068373231&partnerID=8YFLogxK
U2 - 10.23919/LTB-3D.2019.8735115
DO - 10.23919/LTB-3D.2019.8735115
M3 - Conference contribution
AN - SCOPUS:85068373231
T3 - Proceedings of 2019 6th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2019
SP - 17
BT - Proceedings of 2019 6th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2019
Y2 - 21 May 2019 through 25 May 2019
ER -