TY - JOUR
T1 - Multichip self-assembly technology for advanced die-to-wafer 3-D integration to precisely align known good dies in batch processing
AU - Fukushima, Takafumi
AU - Iwata, Eiji
AU - Ohara, Yuki
AU - Murugesan, Mariappan
AU - Bea, Jichoel
AU - Lee, Kangwook
AU - Tanaka, Tetsu
AU - Koyanagi, Mitsumasa
N1 - Funding Information:
Manuscript received October 31, 2010; revised April 18, 2011; accepted May 27, 2011. Date of publication August 8, 2011; date of current version December 21, 2011. This work was supported in part by the Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research 21226009, and by the 60th Electronic Components and Technology Conference, Las Vegas, NV, in 2010. Recommended for publication by Associate Editor M. Bakir upon evaluation of the reviewers’ comments.
PY - 2011/12
Y1 - 2011/12
N2 - An advanced die-to-wafer 3-D integration using a surface-tension-driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5° and 115°. Therefore, various sizes of chips (3 × 3 mm, 5 × 5 mm, 4 × 9 mm, and 10 × 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.
AB - An advanced die-to-wafer 3-D integration using a surface-tension-driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5° and 115°. Therefore, various sizes of chips (3 × 3 mm, 5 × 5 mm, 4 × 9 mm, and 10 × 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.
KW - 3-D integration
KW - alignment and bonding
KW - die-to-wafer stacking
KW - liquid surface tension
KW - self-assembly
UR - http://www.scopus.com/inward/record.url?scp=84859018001&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84859018001&partnerID=8YFLogxK
U2 - 10.1109/TCPMT.2011.2160266
DO - 10.1109/TCPMT.2011.2160266
M3 - Article
AN - SCOPUS:84859018001
VL - 1
SP - 1873
EP - 1884
JO - IEEE Transactions on Components, Packaging and Manufacturing Technology
JF - IEEE Transactions on Components, Packaging and Manufacturing Technology
SN - 2156-3950
IS - 12
M1 - 6119133
ER -