TY - GEN
T1 - Multi-context TCAM based selective computing architecture for a low-power NN
AU - Arakawa, Ren
AU - Onizawa, Naoya
AU - Diguet, Jean Philippe
AU - Hanyu, Takahiro
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by JSPS KAKENHI Grant Numbers JP16H06300 and VLSI Design and Education Center, The University of Tokyo with Synopsys Corpotation.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.
AB - In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.
KW - Convolutional Neural Network
KW - Memory-Based Computing
KW - Multi-Context TCAM
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=85079179600&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85079179600&partnerID=8YFLogxK
U2 - 10.1109/ICECS46596.2019.8964869
DO - 10.1109/ICECS46596.2019.8964869
M3 - Conference contribution
AN - SCOPUS:85079179600
T3 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
SP - 117
EP - 118
BT - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
Y2 - 27 November 2019 through 29 November 2019
ER -
