Multi-context TCAM based selective computing architecture for a low-power NN

Ren Arakawa, Naoya Onizawa, Jean Philippe Diguet, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.

Original languageEnglish
Title of host publication2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages117-118
Number of pages2
ISBN (Electronic)9781728109961
DOIs
Publication statusPublished - 2019 Nov
Event26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 - Genoa, Italy
Duration: 2019 Nov 272019 Nov 29

Publication series

Name2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Conference

Conference26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
CountryItaly
CityGenoa
Period19/11/2719/11/29

Keywords

  • Convolutional Neural Network
  • Memory-Based Computing
  • Multi-Context TCAM
  • VLSI

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Control and Optimization
  • Computer Networks and Communications
  • Hardware and Architecture

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