Multi-context TCAM based selective computing architecture for a low-power NN

Ren Arakawa; Naoya Onizawa; Jean Philippe Diguet; Takahiro Hanyu

doi:10.1109/ICECS46596.2019.8964869

Multi-context TCAM based selective computing architecture for a low-power NN

Ren Arakawa, Naoya Onizawa, Jean Philippe Diguet, Takahiro Hanyu

Systems & Software Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.

Original language	English
Title of host publication	2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	117-118
Number of pages	2
ISBN (Electronic)	9781728109961
DOIs	https://doi.org/10.1109/ICECS46596.2019.8964869
Publication status	Published - 2019 Nov
Event	26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 - Genoa, Italy Duration: 2019 Nov 27 → 2019 Nov 29

Publication series

Name	2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Conference

Conference	26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
Country	Italy
City	Genoa
Period	19/11/27 → 19/11/29

Keywords

Convolutional Neural Network
Memory-Based Computing
Multi-Context TCAM
VLSI

ASJC Scopus subject areas

Electrical and Electronic Engineering
Control and Optimization
Computer Networks and Communications
Hardware and Architecture

UN SDGs

This output contributes to the following Sustainable Development Goal(s)

Access to Document

10.1109/ICECS46596.2019.8964869

Fingerprint Dive into the research topics of 'Multi-context TCAM based selective computing architecture for a low-power NN'. Together they form a unique fingerprint.

Cite this

Arakawa, R., Onizawa, N., Diguet, J. P., & Hanyu, T. (2019). Multi-context TCAM based selective computing architecture for a low-power NN. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (pp. 117-118). [8964869] (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS46596.2019.8964869

Multi-context TCAM based selective computing architecture for a low-power NN. / Arakawa, Ren; Onizawa, Naoya; Diguet, Jean Philippe; Hanyu, Takahiro.

2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 117-118 8964869 (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Arakawa, R, Onizawa, N, Diguet, JP & Hanyu, T 2019, Multi-context TCAM based selective computing architecture for a low-power NN. in 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019., 8964869, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Institute of Electrical and Electronics Engineers Inc., pp. 117-118, 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, 19/11/27. https://doi.org/10.1109/ICECS46596.2019.8964869

Arakawa R, Onizawa N, Diguet JP, Hanyu T. Multi-context TCAM based selective computing architecture for a low-power NN. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 117-118. 8964869. (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019). https://doi.org/10.1109/ICECS46596.2019.8964869

Arakawa, Ren ; Onizawa, Naoya ; Diguet, Jean Philippe ; Hanyu, Takahiro. / Multi-context TCAM based selective computing architecture for a low-power NN. 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 117-118 (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).

@inproceedings{5095fbdea819430da5314e5f5be28920,

title = "Multi-context TCAM based selective computing architecture for a low-power NN",

abstract = "In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.",

keywords = "Convolutional Neural Network, Memory-Based Computing, Multi-Context TCAM, VLSI",

author = "Ren Arakawa and Naoya Onizawa and Diguet, {Jean Philippe} and Takahiro Hanyu",

note = "Funding Information: ACKNOWLEDGMENT This work was supported by JSPS KAKENHI Grant Numbers JP16H06300 and VLSI Design and Education Center, The University of Tokyo with Synopsys Corpotation.; 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 ; Conference date: 27-11-2019 Through 29-11-2019",

year = "2019",

month = nov,

doi = "10.1109/ICECS46596.2019.8964869",

language = "English",

series = "2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "117--118",

booktitle = "2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019",

}

TY - GEN

T1 - Multi-context TCAM based selective computing architecture for a low-power NN

AU - Arakawa, Ren

AU - Onizawa, Naoya

AU - Diguet, Jean Philippe

AU - Hanyu, Takahiro

N1 - Funding Information: ACKNOWLEDGMENT This work was supported by JSPS KAKENHI Grant Numbers JP16H06300 and VLSI Design and Education Center, The University of Tokyo with Synopsys Corpotation.

PY - 2019/11

Y1 - 2019/11

N2 - In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.

AB - In this paper, we propose an energy-efficient hardware architecture that consists of multipliers and a non-volatile Multi-Context Ternary Content-Addressable Memory (MC-TCAM), where a CMOS/magnetic tunnel junction (MTJ) devices-hybrid circuit technique is used. If the input data stored in MC-TCAMs is appeared, the corresponding multiplication result is obtained from the MC-TCAM, resulting in the energy-efficiency. In addition, as the upper bits of the input data could be cut in a target application, the memory capacity of the MC-TCAM becomes small, which reduces power consumption in the MC-TCAMs. In case of speech command recognition, the proposed architecture reduces the power consumption by 45% at the multiplication of a CNN keeping the accuracy using TSMC 65-nm CMOS and a MTJ model.

KW - Convolutional Neural Network

KW - Memory-Based Computing

KW - Multi-Context TCAM

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=85079179600&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85079179600&partnerID=8YFLogxK

U2 - 10.1109/ICECS46596.2019.8964869

DO - 10.1109/ICECS46596.2019.8964869

M3 - Conference contribution

AN - SCOPUS:85079179600

T3 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

SP - 117

EP - 118

BT - 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Y2 - 27 November 2019 through 29 November 2019

ER -

Multi-context TCAM based selective computing architecture for a low-power NN

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

Other files and links

Cite this