MTJ-based nonvolatile ternary logic gate for quantized convolutional neural networks

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A ternary logic gate based on MTJ-based nonvolatile logic-in-memory (NV-LIM) architecture for ternary neural networks (TNNs) is proposed. The NV-LIM-based implementation achieves reduced computational cost and data transfer cost related to the inference function of deep neural networks. Through an experimental evaluation of a basic component of TNNs, its impact on the energy, delay and area overhead reduction is demonstrated.

Original languageEnglish
Title of host publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538676264
DOIs
Publication statusPublished - 2019 Feb 11
Event2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States
Duration: 2018 Oct 152018 Oct 18

Publication series

Name2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
CountryUnited States
CityBurlingame
Period18/10/1518/10/18

Keywords

  • Deep learning
  • MTJ device
  • Nonvolatile logic-in-memory
  • Ternary neural network

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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