MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

Takeshi Honda; Noboru Sakimura; Tadahiko Sugibayashi; Sadahiko Miura; Hideaki Numata; Hiromitsu Hada; Shu Ichi Tahara

MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Sadahiko Miura, Hideaki Numata, Hiromitsu Hada, Shu Ichi Tahara

Research output: Contribution to conference › Paper › peer-review

Abstract

MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.

Original language	English
Pages	156-157
Number of pages	2
Publication status	Published - 2002 Dec 1
Externally published	Yes
Event	2002 Symposium on VLSI Circuits Digest of Technical Papers - Honolulu, HI, United States Duration: 2002 Jun 13 → 2002 Jun 15

Other

Other	2002 Symposium on VLSI Circuits Digest of Technical Papers
Country	United States
City	Honolulu, HI
Period	02/6/13 → 02/6/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current. / Honda, Takeshi; Sakimura, Noboru; Sugibayashi, Tadahiko; Miura, Sadahiko; Numata, Hideaki; Hada, Hiromitsu; Tahara, Shu Ichi.

2002. 156-157 Paper presented at 2002 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, United States.

Research output: Contribution to conference › Paper › peer-review

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abstract = "MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.",

author = "Takeshi Honda and Noboru Sakimura and Tadahiko Sugibayashi and Sadahiko Miura and Hideaki Numata and Hiromitsu Hada and Tahara, {Shu Ichi}",

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AU - Honda, Takeshi

AU - Sakimura, Noboru

AU - Sugibayashi, Tadahiko

AU - Miura, Sadahiko

AU - Numata, Hideaki

AU - Hada, Hiromitsu

AU - Tahara, Shu Ichi

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AB - MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.

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