MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Sadahiko Miura, Hideaki Numata, Hiromitsu Hada, Shu Ichi Tahara

Research output: Contribution to conferencePaper

9 Citations (Scopus)

Abstract

MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current (MRC) is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write (MW) failures from degrading 1Gb MRAM yield where the standard deviation of MRC variation from other origins is less than 5%.

Original languageEnglish
Pages156-157
Number of pages2
Publication statusPublished - 2002 Dec 1
Externally publishedYes
Event2002 Symposium on VLSI Circuits Digest of Technical Papers - Honolulu, HI, United States
Duration: 2002 Jun 132002 Jun 15

Other

Other2002 Symposium on VLSI Circuits Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period02/6/1302/6/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Honda, T., Sakimura, N., Sugibayashi, T., Miura, S., Numata, H., Hada, H., & Tahara, S. I. (2002). MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current. 156-157. Paper presented at 2002 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, United States.