Minimum-latency linear array FFT processor for robotics

Somchai Kittichaikoonkit, Michitaka Kameyama

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In the applications of the fast Fourier transform (FFT) to real-world computation such as robot vision, high-speed processing with small latency is an important issue. In this paper, we propose a linear array processor for the minimum-latency FFT computation. The processor is constructed by identical butterfly elements (BE's). The key concept to minimize the latency is that each BE generates its output data immediately after its input data become available, with 100% utilization of its arithmetic unit. We also introduce the real-valued FFT to perform the complex-valued FFT. We utilize a double linear array structure so that the parallel processing can be realized without communication between the linear arrays. As a result, the hardware amount of a single BE is reduced to half that of conventional designs. The latency of the proposed FFT processor is greatly reduced in comparison with conventional linear array FFT processors.

Original languageEnglish
Pages (from-to)680-688
Number of pages9
JournalIEICE Transactions on Information and Systems
VolumeE76-D
Issue number6
Publication statusPublished - 1993 Jun 1

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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  • Cite this

    Kittichaikoonkit, S., & Kameyama, M. (1993). Minimum-latency linear array FFT processor for robotics. IEICE Transactions on Information and Systems, E76-D(6), 680-688.