One of the most serious reliability issues, the local deformation produced in the stacked LSI die/wafer with respect to the die thickness and the sub-surface structures formed after several stress-relief methods are systematically and extensively studied. From the electron backscatter diffraction (EBSD) analysis, a more than one degree (>1°) of local misorientation is created in the stacked LSI Si around μ-bump region. This induces a large tensile stress above the μ-bump region and relatively small compressive stress in the bump-space region, which leads to an enhancement in the n-MOSFET mobility in the μ-bump region and decrease in mobility at bump-space region. As compared to CuSn system, the InAu μ-bump induced huge amount of tensile stress (> 300 MPa) in the stacked LSI die even for the bonding temperature of 200 °C. The groove structures or scratches found at the background surface after stress relief by plasma etching (PE) or Dry Polishing (DP) severely deteriorates the device characteristics after stacking, owing to the enhanced local deformation as against the stress relief method of chemical mechanical polishing (CMP). Even after 500 cycles of temperature cycle (TC) test, a 20 μm-width Cu-TSV array with 40- μm pitch values induces not only around -570 MPa of compressive stress in the stacked LSI die, but also a large variation in the induced stress values between different TSVs in the same array. For the LSI die/wafer thickness of anything less than 50 μm, the Young modulus (E) and Hardness (H) of the thinned die no longer behaves like a bulk single crystal Si, which severely increases the reliability risks in the highly integrated 3D-LSIs.