Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification

Masanori Hariyama; Shigeo Yamadera; Michitaka Kameyama

doi:10.1109/MWSCAS.2005.1594488

Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification

Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a design method to minimize energy of both functional units (FUs) and an interconnection network between FUs. To reduce complexity of the interconnection network, data transfers between FUs are classified according to FU types of operations in a data flow graph. The basic idea behind reducing the complexity of the interconnection network is that the interconnection resource can be shared among data transfers with the same FU type of a source node and the same FU type of a destination node. Moreover, an efficient method based on a genetic algorithm is presented for large-size problems.

Original language	English
Title of host publication	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages	1867-1870
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2005.1594488
Publication status	Published - 2005 Dec 1
Event	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States Duration: 2005 Aug 7 → 2005 Aug 10

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2005
ISSN (Print)	1548-3746

Other

Other	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Country	United States
City	Cincinnati, OH
Period	05/8/7 → 05/8/10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2005.1594488

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Hariyama, M., Yamadera, S., & Kameyama, M. (2005). Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification. In 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 (pp. 1867-1870). [1594488] (Midwest Symposium on Circuits and Systems; Vol. 2005). https://doi.org/10.1109/MWSCAS.2005.1594488

Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification. / Hariyama, Masanori; Yamadera, Shigeo; Kameyama, Michitaka.

2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005. 2005. p. 1867-1870 1594488 (Midwest Symposium on Circuits and Systems; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hariyama, M, Yamadera, S & Kameyama, M 2005, Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification. in 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005., 1594488, Midwest Symposium on Circuits and Systems, vol. 2005, pp. 1867-1870, 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, Cincinnati, OH, United States, 05/8/7. https://doi.org/10.1109/MWSCAS.2005.1594488

@inproceedings{5122c78c0bc5486c9a3d2d28b5125fc8,

title = "Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification",

abstract = "This paper presents a design method to minimize energy of both functional units (FUs) and an interconnection network between FUs. To reduce complexity of the interconnection network, data transfers between FUs are classified according to FU types of operations in a data flow graph. The basic idea behind reducing the complexity of the interconnection network is that the interconnection resource can be shared among data transfers with the same FU type of a source node and the same FU type of a destination node. Moreover, an efficient method based on a genetic algorithm is presented for large-size problems.",

author = "Masanori Hariyama and Shigeo Yamadera and Michitaka Kameyama",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/MWSCAS.2005.1594488",

language = "English",

isbn = "0780391977",

series = "Midwest Symposium on Circuits and Systems",

pages = "1867--1870",

booktitle = "2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005",

note = "2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 ; Conference date: 07-08-2005 Through 10-08-2005",

}

TY - GEN

T1 - Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification

AU - Hariyama, Masanori

AU - Yamadera, Shigeo

AU - Kameyama, Michitaka

PY - 2005/12/1

Y1 - 2005/12/1

N2 - This paper presents a design method to minimize energy of both functional units (FUs) and an interconnection network between FUs. To reduce complexity of the interconnection network, data transfers between FUs are classified according to FU types of operations in a data flow graph. The basic idea behind reducing the complexity of the interconnection network is that the interconnection resource can be shared among data transfers with the same FU type of a source node and the same FU type of a destination node. Moreover, an efficient method based on a genetic algorithm is presented for large-size problems.

AB - This paper presents a design method to minimize energy of both functional units (FUs) and an interconnection network between FUs. To reduce complexity of the interconnection network, data transfers between FUs are classified according to FU types of operations in a data flow graph. The basic idea behind reducing the complexity of the interconnection network is that the interconnection resource can be shared among data transfers with the same FU type of a source node and the same FU type of a destination node. Moreover, an efficient method based on a genetic algorithm is presented for large-size problems.

UR - http://www.scopus.com/inward/record.url?scp=33847162906&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847162906&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2005.1594488

DO - 10.1109/MWSCAS.2005.1594488

M3 - Conference contribution

AN - SCOPUS:33847162906

SN - 0780391977

SN - 9780780391970

T3 - Midwest Symposium on Circuits and Systems

SP - 1867

EP - 1870

BT - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005

T2 - 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005

Y2 - 7 August 2005 through 10 August 2005

ER -