Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification

Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a design method to minimize energy of both functional units (FUs) and an interconnection network between FUs. To reduce complexity of the interconnection network, data transfers between FUs are classified according to FU types of operations in a data flow graph. The basic idea behind reducing the complexity of the interconnection network is that the interconnection resource can be shared among data transfers with the same FU type of a source node and the same FU type of a destination node. Moreover, an efficient method based on a genetic algorithm is presented for large-size problems.

Original languageEnglish
Title of host publication2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages1867-1870
Number of pages4
DOIs
Publication statusPublished - 2005 Dec 1
Event2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States
Duration: 2005 Aug 72005 Aug 10

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2005
ISSN (Print)1548-3746

Other

Other2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
CountryUnited States
CityCincinnati, OH
Period05/8/705/8/10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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