TY - GEN
T1 - Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission
AU - Kino, Hisashi
AU - Tashiro, Masataka
AU - Sugawara, Yohei
AU - Tanikawa, Seiya
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/5
Y1 - 2017/7/5
N2 - Through-Si-via (TSV) with polymer liner formation has attracted considerable attention because a polymer liner can be formed easily by spin coating, and it has low dielectric constant and good coverage along the TSV surface. A polyimide (PI) was used as the polymer liner of TSV. However, there is a high charge-trap density in the PI layer. These charge traps leads to modulation of the parasitic capacitance present between the TSV metal and the Si substrate. Therefore, in this paper, we propose the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structure was fabricated with PBO and PI liners. Further, capacitance-voltage (C-V) characteristics of the fabricated MOS capacitor were evaluated. In case of the PBO liner, remarkable suppression of the C-V curve shift was observed as compared to that of the PI liner. These results indicate that the PBO is a promising TSV liner material for realizing high-performance, high-reliability, and low-cost three-dimensional stacked ICs.
AB - Through-Si-via (TSV) with polymer liner formation has attracted considerable attention because a polymer liner can be formed easily by spin coating, and it has low dielectric constant and good coverage along the TSV surface. A polyimide (PI) was used as the polymer liner of TSV. However, there is a high charge-trap density in the PI layer. These charge traps leads to modulation of the parasitic capacitance present between the TSV metal and the Si substrate. Therefore, in this paper, we propose the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structure was fabricated with PBO and PI liners. Further, capacitance-voltage (C-V) characteristics of the fabricated MOS capacitor were evaluated. In case of the PBO liner, remarkable suppression of the C-V curve shift was observed as compared to that of the PI liner. These results indicate that the PBO is a promising TSV liner material for realizing high-performance, high-reliability, and low-cost three-dimensional stacked ICs.
KW - 3D IC
KW - PBO
KW - TSV
KW - charge trap
KW - polymer liner
UR - http://www.scopus.com/inward/record.url?scp=85027137236&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85027137236&partnerID=8YFLogxK
U2 - 10.1109/IITC-AMC.2017.7968936
DO - 10.1109/IITC-AMC.2017.7968936
M3 - Conference contribution
AN - SCOPUS:85027137236
T3 - IITC 2017 - 2017 IEEE International Interconnect Technology Conference
BT - IITC 2017 - 2017 IEEE International Interconnect Technology Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE International Interconnect Technology Conference, IITC 2017
Y2 - 16 May 2017 through 18 May 2017
ER -