Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration

Jichoru Be, M. Murugesan, Y. Ohara, A. Noriki, Hisashi Kino, Kanuku Ri, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5°) polished silicon wafers by micro-Raman spectroscopy (μRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffus ed with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro-bump in 3D LSI.

Original languageEnglish
Title of host publication2009 IEEE International Conference on 3D System Integration, 3DIC 2009
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 IEEE International Conference on 3D System Integration, 3DIC 2009 - San Francisco, CA, United States
Duration: 2009 Sep 282009 Sep 30

Publication series

Name2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Other

Other2009 IEEE International Conference on 3D System Integration, 3DIC 2009
CountryUnited States
CitySan Francisco, CA
Period09/9/2809/9/30

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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