Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration

Jichoru Be; M. Murugesan; Y. Ohara; A. Noriki; Hisashi Kino; Kanuku Ri; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi

doi:10.1109/3DIC.2009.5306568

Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration

Jichoru Be, M. Murugesan, Y. Ohara, A. Noriki, Hisashi Kino, Kanuku Ri, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5°) polished silicon wafers by micro-Raman spectroscopy (μRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffus ed with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro-bump in 3D LSI.

Original language	English
Title of host publication	2009 IEEE International Conference on 3D System Integration, 3DIC 2009
DOIs	https://doi.org/10.1109/3DIC.2009.5306568
Publication status	Published - 2009 Dec 1
Event	2009 IEEE International Conference on 3D System Integration, 3DIC 2009 - San Francisco, CA, United States Duration: 2009 Sep 28 → 2009 Sep 30

Publication series

Name	2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Other

Other	2009 IEEE International Conference on 3D System Integration, 3DIC 2009
Country/Territory	United States
City	San Francisco, CA
Period	09/9/28 → 09/9/30

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/3DIC.2009.5306568

Cite this

Be, J., Murugesan, M., Ohara, Y., Noriki, A., Kino, H., Ri, K., Fukushima, T., Tanaka, T., & Koyanagi, M. (2009). Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. In 2009 IEEE International Conference on 3D System Integration, 3DIC 2009 [5306568] (2009 IEEE International Conference on 3D System Integration, 3DIC 2009). https://doi.org/10.1109/3DIC.2009.5306568

Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. / Be, Jichoru; Murugesan, M.; Ohara, Y. et al.

2009 IEEE International Conference on 3D System Integration, 3DIC 2009. 2009. 5306568 (2009 IEEE International Conference on 3D System Integration, 3DIC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Be, J, Murugesan, M, Ohara, Y, Noriki, A, Kino, H, Ri, K, Fukushima, T , Tanaka, T & Koyanagi, M 2009, Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. in 2009 IEEE International Conference on 3D System Integration, 3DIC 2009., 5306568, 2009 IEEE International Conference on 3D System Integration, 3DIC 2009, 2009 IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, CA, United States, 09/9/28. https://doi.org/10.1109/3DIC.2009.5306568

Be J, Murugesan M, Ohara Y, Noriki A, Kino H, Ri K et al. Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. In 2009 IEEE International Conference on 3D System Integration, 3DIC 2009. 2009. 5306568. (2009 IEEE International Conference on 3D System Integration, 3DIC 2009). https://doi.org/10.1109/3DIC.2009.5306568

@inproceedings{d8d9ad1abbd04e2cb41cd337719441dd,

title = "Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration",

abstract = "Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5°) polished silicon wafers by micro-Raman spectroscopy (μRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffus ed with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro-bump in 3D LSI.",

author = "Jichoru Be and M. Murugesan and Y. Ohara and A. Noriki and Hisashi Kino and Kanuku Ri and Takafumi Fukushima and Tetsu Tanaka and Mitsumasa Koyanagi",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/3DIC.2009.5306568",

language = "English",

isbn = "9781424445127",

series = "2009 IEEE International Conference on 3D System Integration, 3DIC 2009",

booktitle = "2009 IEEE International Conference on 3D System Integration, 3DIC 2009",

note = "2009 IEEE International Conference on 3D System Integration, 3DIC 2009 ; Conference date: 28-09-2009 Through 30-09-2009",

}

TY - GEN

T1 - Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration

AU - Be, Jichoru

AU - Murugesan, M.

AU - Ohara, Y.

AU - Noriki, A.

AU - Kino, Hisashi

AU - Ri, Kanuku

AU - Fukushima, Takafumi

AU - Tanaka, Tetsu

AU - Koyanagi, Mitsumasa

PY - 2009/12/1

Y1 - 2009/12/1

N2 - Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5°) polished silicon wafers by micro-Raman spectroscopy (μRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffus ed with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro-bump in 3D LSI.

AB - Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5°) polished silicon wafers by micro-Raman spectroscopy (μRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffus ed with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro-bump in 3D LSI.

UR - http://www.scopus.com/inward/record.url?scp=70549109018&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70549109018&partnerID=8YFLogxK

U2 - 10.1109/3DIC.2009.5306568

DO - 10.1109/3DIC.2009.5306568

M3 - Conference contribution

AN - SCOPUS:70549109018

SN - 9781424445127

T3 - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009

BT - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009

T2 - 2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Y2 - 28 September 2009 through 30 September 2009

ER -

Micro-raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this