Metal inserted poly-Si with high temperature annealing for achieving EOT of 0.62nm in La-silicate MOSFET

T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm-2 eV -1 can be achieved by annealing at 800°C for 30min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibited with MIPS stacks accompanied by high quality interface. The effective electron mobility of 155 cm2/Vsec at 1MV/cm with an EOT of 0.62 nm has been obtained in direct contact La-silicate/Si structure by combination of MIPS stacks with high temperature annealing.

Original languageEnglish
Title of host publicationESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference
Pages67-70
Number of pages4
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event41st European Solid-State Device Research Conference, ESSDERC 2011 - Helsinki, Finland
Duration: 2011 Sep 122011 Sep 16

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Other

Other41st European Solid-State Device Research Conference, ESSDERC 2011
Country/TerritoryFinland
CityHelsinki
Period11/9/1211/9/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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