Memory hierarchy design for jetpipeline: to execute scalar and vector instructions in parallel

Takehito Sasaki, Takuya Nakaike, Koji Takano, Masayuki Katahira, Hiroaki Kobayashi, Tadao Nakamura

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

Superscalar and VLIW architectures are based on instruction-level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architecture. We have proposed a computer architecture named Jetpipeline, which can execute both vector and scalar instructions in parallel. To make full use of the computing ability of Jetpipeline, this paper presents the memory hierarchy design for Jetpipeline and evaluates the effect of the design on the system performance of Jetpipeline through simulations.

Original languageEnglish
Pages66-73
Number of pages8
Publication statusPublished - 1997 Jan 1
EventProceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis - Fukushima, Jpn
Duration: 1997 Mar 171997 Mar 21

Other

OtherProceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
CityFukushima, Jpn
Period97/3/1797/3/21

ASJC Scopus subject areas

  • Computer Science(all)

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