Memory design using one-transistor gain cell on SOI

Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

    Research output: Contribution to journalConference article

    Abstract

    A 512 kb DRAM has a 7F2 one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

    Original languageEnglish
    Pages (from-to)114-115+425
    JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    Issue numberSUPPL.
    Publication statusPublished - 2002 Jan 1
    Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
    Duration: 2002 Feb 32002 Feb 7

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Ohsawa, T., Fujita, K., Higashi, T., Iwata, Y., Kajiyama, T., Asao, Y., & Sunouchi, K. (2002). Memory design using one-transistor gain cell on SOI. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, (SUPPL.), 114-115+425.